High Density Chip Interconnect Technology

Grant applications are sought for the development of new technologies for reducing cost while increasing the density of interconnection of pixelated sensors to readout electronics by enhancing or replacing solder bump-based technologies. Development of cost-effective technologies to connect arrays of thinned integrated circuits (< 50 microns, with areas of ~2x2 cm^2) to high-resistivity silicon sensors with interconnect pitch of 50 microns or less are of interest. Technologies are sought that can minimize dead regions at device edges and/or enable wafer-to-wafer interconnection, by utilizing 3D integration with through-silicon vias or other methods.